5.2d Maximizing Clock Frequency

Clock Period Constraint

The clock frequency inequality ensures reliable operation of sequential digital circuits by requiring that the clock period $T_{clk}$ be sufficiently long to account for various timing requirements. Formally, this is expressed as
$T_{\text{clk}}\ge t_{\text{clk-to-q}}+t_{\text{longest-comb}}+t_{\text{setup}},$
where $t_{\text{setup}}$ is the setup time of the flip-flop, $t_{\text{clk-to-q}}$ is the clock-to-Q delay, and $t_{\text{longest-comb}}$ is the path with the longest propagation delay between the flip-flops in a digital circuit.

Note! critical path of a digital circuit.

The three components above form the

Understanding