RISC-V 5-Stage Datapath
The RISC-V 5-stage datapath is a simplified representation of a pipeline used in RISC-V processors when executing instructions. It consists of the following stages:
- Instruction Fetch (IF): the instruction is fetched from memory, and the program counter (PC) is updated to point to the next line of code.
- Instruction Decode (ID): the fetched instruction is decoded (its type is determined).
- Execute (EX): respective calculations are performed. This may include arithmetic and logic operations, or the calculation of the effective address for memory instructions.
- Memory Access (MEM): data is read from or written to memory. This only applies to load/store instructions.
- Write Back (WB): if any registers are modified, the result of the instruction is written back into the register file.
The RISC-V datapath is as shown in the figure below:
Note! PC and RegFile using PCSel and ALUSel respectively are both part of the Write Back stage.
Writes to