5-Stage Datapath Pipelining
Datapath pipelining is a technique used in computer architecture to increase the instruction throughput of a processor. In RISC-V, the 5 datapath stages are divided by the addition of clocked registers at every stage, allowing multiple instructions to be executed at the same time:
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Note!
When pipelining the datapath, we separate the index of the destination (write) register from the rest of the RegFile inputs to account for parallel instructions by making sure that it is the destination register of the instruction in the Write Back stage that gets written to.