2.6b.2 Data Hazards

RISC-V Data Hazards

In the RISC-V datapath, data hazards occur when an instruction is dependent on the result of a previous instruction, such as two operations which (1) perform an arithmetic operation, and (2) save the output of that operation to memory.

Data hazards can be solved by:

• Stalling, by waiting for the first instruction to write its result before the second instruction reads it using nop (no-op) instructions (such as add x0 x0 x0), which do not have any intrinsic value, but add extra overhead to our code.
  • This approach varies depending on whether the register file implements double pumping, where a new value is read by an instruction in the same cycle it was written to a register by another instruction.
• Forwarding, by adding extra hardware (logic) to send the result back to earlier stages before the result is written.
• Code scheduling, by rearranging

Examples

RISC-V

Suppose we currently have the following RISC-V instructions in our pipeline:

| Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| :------------: | :-: | :-: | :-: | :----: | :----: | :----: | :-: |
| add t0 t1 t2 | IF | ID | EX | M | WB | | |
| or t3 t4 t5 | | IF | ID | EX | M | WB | |
| slt t6 t0 t3 | | | IF | ID | EX | M | WB |
There is a clear data hazard in this pipeline, as slt reads registers t0 and t3 before the results of the first two operations are written to them. However, we can address this.

Stalling nops. Then, if the register file supports double pumping:

One way we can do so is by stalling using

| Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
| :------------: | :-: | :-: | :-: | :-: | :----: | :----: | :-: | :-: | :-: |
| add t0 t1 t2 | IF | ID | EX | M | WB | | | | |
| or t3 t4 t5 | | IF | ID | EX | M | WB | | | |
| add x0 x0 x0 | | | IF | ID | EX | M | WB | | |
| add x0 x0 x0 | | | | IF | ID | EX | M | WB | |
| slt t6 t0 t3 | | | | | IF | ID | EX | M | WB |
Note how the decode stage of the slt instruction overlaps with the write-back stage of the or instruction. If double pumping was not implemented, then we would need one additional nop, such that or writing back precedes slt decoding.

Forwarding or computed by the ALU in the $4$-th cycle and using extra logic to forward it to the execution stage of the slt operation by the $5$-th cycle: INSERT IMAGE OF FORWARDED DATAPATH

We can also address this data hazard by forwarding. This would require taking the value of

Code Scheduling lw a0 4(a0) and addi s4 x0 5. Then, we can rearrange our code such that:

Instead of filling space with nops, we can reorder our code to avoid data hazards. Suppose right after our snippet, we have additional instructions (which are not dependent on previous instructions):

| Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
| :------------: | :-: | :-: | :-: | :-: | :----: | :----: | :-: | :-: | :-: |
| add t0 t1 t2 | IF | ID | EX | M | WB | | | | |
| or t3 t4 t5 | | IF | ID | EX | M | WB | | | |
| addi s4 x0 5 | | | IF | ID | EX | M | WB | | |
| lw a0 4(a0) | | | | IF | ID | EX | M | WB | |
| slt t6 t0 t3 | | | | | IF | ID | EX | M | WB |
In this example, we again consider that the RegFile supports double pumping.